1. Technical Field
The present disclosure relates to a semiconductor memory device, in particular, to a method for reducing the standby current of the semiconductor memory device.
2. Description of Related Art
In the dynamic semiconductor memory device, for example, dynamic random access memory (DRAM), a bit line/word line short-circuiting defect, that is, a cross-fail defect, is liable to occur due to the microminiaturization and high integration density of elements. To overcome operation errors due to the cross-fail, the conventional semiconductor memory device may have a repairing circuit, that is, a redundancy circuit. The repairing circuit has the spare bit lines and word lines to replace the defective bit lines and word lines, and thus a yield rate of the semiconductor memory device can be improved.
Generally speaking, the repairing circuit has at least one redundant row of spare bit lines and at least one column of spare word lines, and thus the space of the semiconductor memory device is increased. Furthermore, though the cross-fail may be remedied by the repairing circuit, the defective word lines and bit lines associated with the cross-fail are still not electrically separated. Thus, when the semiconductor memory device operates in the standby mode, that is, at a precharging time, the cross-fail increases the standby current, causing a standby failure.
One approach to minimizing current flow due to the cross-fail is the use of a pulsed equalizer control while enabling the precharge equalizer signal. This scheme, however allows a floating state in each bit-line pair, causing a bit-line voltage drift in a long pause condition. To avoid this problem, a reference cell is provided for bit-line sensing. Such the reference cell, however, requires a complicated layout, difficult control, and a large active current dissipation.
Referring to FIG. 1, FIG. 1 is an equivalent circuit diagram showing a conventional semiconductor memory device which has a cross-fail. The semiconductor memory device 1 comprises at least a memory cell, a sensing amplifier 12, and a precharge circuit implemented by the PMOS transistors P1, P2, and the NMOS transistor N1. When the cross-fail occurs at the word line WL1 and the line BL, the bit line/word line short circuiting 11 can be modeled a resistor between the word line WL1 and the bit line BL.
In FIG. 1, a source and a drain of the NMOS transistor N1 are respectively coupled to the bit lines BL and /BL of the bit line pair, and a gate of the NMOS transistor receives a first control signal BLEQ. Two ends of the sensing amplifier 12 are coupled to the bit lines BL and /BL of the bit line pair. Two source of the PMOS transistors P1 and P2 are coupled to an equalizing voltage Veq. Two drains of the PMOS transistors P1 and P2 are respectively coupled to the bit lines BL and /BL of the bit line pair. Two gates of the PMOS transistors P1 and P2 receive a second control signal BLEQB.
Referring to FIG. 1 and FIG. 2, FIG. 2 is a waveform diagram of a row address strobe signal, a word line signal, a first control signal, and a second control signal in the conventional semiconductor memory device of FIG. 1. The row address strobe signal /RAS controls the semiconductor memory device 1 to operate in the standby mode or the active mode. The word line signal WL is used to select the corresponding word line, for example the word line WL1. The first and second control signals BLEQ and BLEQB are used to control the precharge circuit to precharge the bit lines BL and /BL of the bit line pair in the standby mode.
Firstly, the row address strobe signal /RAS is at a logic high level, thus the semiconductor memory device 1 operates in the standby mode, and the word line signal WL is at a logic low level. The first control signal BLEQ is at the logic high level, the second control signal BLEQB is at a second logic low level, and thus the PMOS transistors P1, P2 and the NMOS transistor N1 are turned on. Since the cross-fail occurs, leak currents Ileak1 and Ileak2 are aggregated to form a standby current Ileak—prior which passes through the bit line/word line short circuiting 11.
Then, the row address strobe signal /RAS changes from the logic high level to the logic low level, thus the semiconductor memory device 1 start to operate in the active mode. When the semiconductor memory device 1 start to operate in the active mode, the first and second control signals BLEQ and BLEQB respectively maintain the logic high and the second logic low levels for a period T1′, wherein the period T1′ is much shorter than the period of the active mode. After first and second control signals BLEQ and BLEQB have respectively maintained the logic high and the second logic low levels for the period T1′, the first control signal BLEQ changes from the logic high level to the logic low level, and the second control signal BLEQB changes from the second logic low level to a first logic high level. After the first and second control signals BLEQ and BLEQB have been at the logic low and first logic high levels, the word line signal WL changes from the logic low level to the logic high level. It is noted that, the logic high level can be the first logic high level, the logic low level can be the first or second logic low level (the first logic low level is lower than the second logic level), and the present disclosure is not limited thereto.
Next, the row address strobe signal /RAS changes from the logic low level to the logic high level, and thus the semiconductor memory device 1 start to operate in the standby mode again. Before the first control signal BLEQ changes from the logic low level and the logic high level, and the second control signal BLEQB changes from the first logic high level to the second logic low level, the word line signal WL changes from the logic high level to the logic low level. After the word line signal has changed from the logic high level to the logic low level, the first control signal BLEQ changes from the logic low level to the logic low level, and the second control signal BLEQB changes from the first logic high level to the first logic low level. After the second control signal BLEQB has maintained the first logic low level for the transient period T2′, the second control signal BLEQB changes from the first logic low level to the a second logic low level, and the first control signal BLEQ still maintains the logic high level, wherein the second logic low level higher than the first logic low level, and the transient period T2′ is much shorter than the period of the standby mode. Thus, the PMOS transistors P1, P2, and the NMOS transistor N1 are still turned on. The second control signal BLEQB with the second logic low level is used to improve the precharge of the bit lines BL and /BL, and there is still the standby current Ileak—prior passing through the bit line/word line short circuiting 11.
Next, the row address strobe signal /RAS changes from the logic high level to the logic low level, and thus the semiconductor memory device 1 start to operate in the active mode again. When the semiconductor memory device 1 start to operate in the active mode again, the first and second control signals BLEQ and BLEQB respectively maintain the logic high and the second logic low levels for a period T1′. After first and second control signals BLEQ and BLEQB have respectively maintained the logic high and the second low levels for the period T1′, the first control signal BLEQ changes from the logic high level to the logic low level, and the second control signal BLEQB changes from the second logic low level to the first logic high level.